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- Path: Concord01.pop.internex.net!usenet
- From: Kevin Braun <kevinb@tutsys.com>
- Newsgroups: comp.sys.m68k
- Subject: 68302 DRAM Refresh & External Masters
- Date: Mon, 08 Jan 96 16:48:44 PDT
- Organization: InterNex Information Services 1-800-595-3333
- Message-ID: <NEWTNews.821149036.27321.kevinb@king.tutsys.com>
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- Hi all,
- I am looking for signal timing and sequence for using the '302's DRAM refresh
- with asynchronous bus masters (i.e. 83902 Ethernet MAC). This subject doesn't
- seem to be covered in the data book. While the 83902 is mastering, it can hold
- the bus for a number of refresh cycles. I don't see any way of using !BCLR to
- stop the 83902 from releasing the bus before it wants to. Does anyone have any
- experience in this area or point me to some reference material? Thanks
-
- ..kevin braun
-
-